Bridge

Parameter-based customized interface for use with 10 different protocols including PCIe and AXI

Hardware Devices

  • DMA
    Table-based customized DMA for use with and without a CPU
  • Bridge
    Parameter-based customized interface for use with 10 different protocols including PCIe and AXI
  • Switch/Crossbar/Serial Switch
    Backbone switch for use in SoC and systems
  • FPGA
    Multiple generations of Xiling FPGA including Virtex 4, Zynq 7000 and Ultrascale
  • Clock Tree
    Simulate Jitters To Clock Tree Modeling
  • USART
    Synchronous and asynchronous receiver-transmitter
  • Hardware-in-the-Loop
    Interface to instruments and FPGA boards for connecting to data sources, hardware and software executing code

Quick Explanation

  • Supports connection between multiple buses
  • Supports cases where the connected devices doesn’t have a routing table entry

Model Link

Bridge

The Bridge block is used to connect two buses together. The VisualSim Bridge module offers the fundamental requirements for making a connection between multiple buses for constructing a comprehensive model. This block is unique and support protocol conversions across both standard-specific and generic buses. These include AXI, CHI, ACE, PCI, AHB, PCIe and Ethernet.

Features

Parameters include Bridge speed, Bridge Width and Overhead Cycles.

Working and Usage

  • Input and Output connections from one device must be on the same side.
  • Bridge block connects two network segments, typically by operating transparently and deciding on a frame-by-frame basis whether or not to forward from one network to the other.

Bridge- Processor fetches data by accessing Bus_2 trough the bridge